all: clean compile simulate

compile:
	iverilog -o ./build/simv \
	./tb_LC3.v \
	./mux16_4to1.v \
	./mux16_8to1.v \
	./mux_2to1.v \
	./half_adder.v \
	./full_adder.v \
	./add_16.v \
	./ALU_3basic_fixed.v \
	./register_16.v \
	./register_mine.v \
	./ram.v \
	./pc.v \
	./pc_reg.v \
	./FSM.v \
	./LC_3.v  \
	./tristate.v \
	./decoder_3to8.v \
	./DFF.v
	
simulate:
	vvp -n ./build/simv #vvp为仿真语句，会生成测试激励中所规定的vcd文件
	
gtkwave:
	gtkwave tb_****.vcd


clean:
	rm -rf cs*
	rm -rf ./build/simv
	#rm -rf ./src/D_latch.v.out #可以不写省略这一行，因为已经把v.out文件命名为simv文件了，故不会生成v.out文件
